1. Field of the Invention
The present invention relates to on-chip circuits for checking and testing integrated circuits, and more particularly to a circuit for on-line, testable self-checking of a differential cascode voltage switch.
2. Description of the Prior Art
U.S. Pat. No. 4,410,816 issued to Kanai on Oct. 18, 1983 and entitled ECL INTEGRATED CIRCUIT describes an ECL integrated circuit which comprises an emitterfollower transistor at the output stage and a pull-down resistor connected to the emitter-follower transistor. The ECL integrated circuit is provided with a test circuit on a line extending from the output of emitter-follower transistor to a subsequent stage so as to cause a test current to flow only at the time of the test. The test current is smaller than the current usually flowing to the pull-down resistor but larger than the current flowing to the subsequent stage.
U.S. Pat. No. 4,183,460 issued to Yuen et al on Jan. 15, 1980 and entitled IN-SITU TEST AND DIAGNOSTIC CIRCUITRY AND METHOD FOR CML CHIPS teaches the use of an in situ test and diagnostic circuit to monitor the integrity of external connections of a current mode logic integrated circuit chip (inputs and outputs) as well as the integrity of the logic function thereof. The circuit comprises three parts: an "open" input detector to detect open connections or connections that are becoming open between one chip and another; an output short detector to monitor shorts at any chip output; and a signature test and diagnostic circuit to determine if the logic function of the chip itself is operational. All the foregoing circuit parts are formed as an integral part of each CML chip and connected to an output terminal called a test and diagnostic pin.
U.S. Pat. No. 4,339,710 issued to Hapke on July 13, 1982 and entitled MOS INTEGRATED TEST CIRCUIT USING FIELD EFFECT TRANSISTORS describes an MOS integrated circuit arrangement with field-effect transistors including a circuit arrangement for rapidly testing various blocks of the circuit. This circuit arrangement includes three transistor-switch groups; a first group for testing an input block, a second group for connecting and disconnecting the input block and an output block so that the blocks may be tested in combination, and a third group for testing the output block.